Abstract

An Efficient Multi-processor Architecture for Parallel Cyclic Reference Counting
Rafael Lins - Departamento de Eletrônica e Sistemas, CTG, Universidade Federal de Pernambuco
Multi-processor architectures are part of the technological reality of today. On the other hand, the software engineering community reached the consensus that memory management has to be performed automatically, without the interference of the programmer of applications. eference counting is the memory management technique of most widespread use today. This paper presents a new architecture for parallel cyclic reference counting.

An Efficient Multi-processor Architecture for Parallel Cyclic Reference Counting

Rafael Lins - Departamento de Eletrônica e Sistemas, CTG, Universidade Federal de Pernambuco

Multi-processor architectures are part of the technological reality of today.

On the other hand, the software engineering community reached the consensus 
that memory management has to be performed automatically, without the
interference 
of the programmer of applications. 
eference counting is the memory management technique of most widespread use
today. 
This paper presents a new architecture for parallel cyclic reference counting.

Last update: Wed Jun 12 14:26:53 2002 WEST